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? 2000 fairchild semiconductor corporation ds500098 www.fairchildsemi.com february 1998 revised july 2000 74vhc161284 ieee 1284 transceiver 74vhc161284 ieee 1284 transceiver general description the vhc161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full ieee 1284 compliant interface. the device supports the ieee 1284 standard and is intended to be used in extended capabilities port mode (ecp). the pinout allows for easy connection from the peripheral (a-side) to the host (cable side). outputs on the cable side can be configured to be either open drain or high drive ( 14 ma). the pull-up and pull- down series termination resistance of these outputs on the cable side is optimized to drive an external cable. in addi- tion, all inputs (except hlh) and outputs on the cable side contain internal pull-up resistors connected to the v cc sup- ply to provide proper termination and pull-ups for open drain mode. outputs on the peripheral side are standard low-drive cmos outputs. the dir input controls data flow on the a 1 ?a 8 /b 1 ?b 8 transceiver pins. features supports ieee 1284 level 1 and level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals replaces the function of two (2) 74act1284 devices all inputs have hysteresis to provide noise margin b and y output resistance optimized to drive external cable b and y outputs in high impedance mode during power down inputs and outputs on cable side have internal pull-up resistors flow-through pin configuration allows easy interface between the peripheral and host ordering code: surface mount packages are also available on tape and reel. specify by appending the suffix letter ? x ? to the ordering code. logic symbol connection diagram ordering number package number package description 74vhc161284mea ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300 wide 74vhc161284mtd mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 74vhc161284 pin descriptions truth table note 1: y 9 ? y 13 open drain outputs note 2: b 1 ? b 8 open drain outputs logic diagram pin names description hd high drive enable input (active high) dir direction control input a 1 ? a 8 inputs or outputs b 1 ? b 8 inputs or outputs a 9 ? a 13 inputs y 9 ? y 13 outputs a 14 ? a 17 outputs c 14 ? c 17 inputs plh in peripheral logic high input plh peripheral logic high output hlh in host logic high input hlh host logic high output inputs outputs dir hd llb 1 ? b 8 data to a 1 ? a 8 , and a 9 ? a 13 data to y 9 ? y 13 (note 1) c 14 ? c 17 data to a 14 ? a 17 plh open drain mode lhb 1 ? b 8 data to a 1 ? a 8 , and a 9 ? a 13 data to y 9 ? y 13 c 14 ? c 17 data to a 14 ? a 17 hla 1 ? a 8 data to b 1 ? b 8 (note 2) a 9 ? a 13 data to y 9 ? y 13 (note 1) c 14 ? c 17 data to a 14 ? a 17 plh open drain mode hha 1 ? a 8 data to b 1 ? b 8 a 9 ? a 13 data to y 9 ? y 13 c 14 ? c 17 data to a 14 ? a 17
3 www.fairchildsemi.com 74vhc161284 absolute maximum ratings (note 3) recommended operating conditions note 3: absolute maximum continuos ratings are those values beyond which damage to the device may occur. exposure to these indicated may adversely affect device reliability. functional operation under absolute max- imum rated conditions is not implied. note 4: either voltage limit or current limit is sufficient to protect inputs. dc electrical characteristics supply voltage v cc ? 0.5v to + 7.0v input voltage (v i ) (note 4) a 1 ? a 13 , plh in , dir, hd ? 0.5v to v cc + 0.5v b 1 ? b 8 , c 14 ? c 17 , hlh in ? 0.5v to + 5.5v (dc) b 1 ? b 8 , c 14 ? c 17 , hlh in ? 2.0v to + 7.0v * *40 ns transient output voltage (v o ) a 1 ? a 8 , a 14 ? a 17 , hlh ? 0.5v to v cc + 0.5v b 1 ? b 8 , y 9 ? y 13 , plh ? 0.5v to + 5.5v (dc) b 1 ? b 8 , y 9 ? y 13 , plh ? 2.0v to + 7.0v* *40 ns transient dc output current (i o ) a 1 ? a 8 , hlh 25 ma b 1 ? b 8 , y 9 ? y 13 50 ma plh (output low) 84 ma plh (output high) ? 50 ma input diode current (i ik ) (note 4) dir, hd, a 9 ? a 13 , plh, hlh, c 14 ? c 17 ? 20 ma output diode current (i ok ) a 1 ? a 8 , a 14 ? a 17 , hlh 50 ma b 1 ? b 8 , y 9 ? y 13 , plh ? 50 ma dc continuous v cc or ground current 200 ma storage temperature ? 65 c to + 150 c esd (hbm) last passing voltage 2000v supply voltage v cc 4.5v to 5.5v dc input voltage (v i ) 0v to v cc open drain voltage (v o ) 0v to 5.5v operating temperature (t a ) ? 40 c to + 85 c symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) guaranteed limits v ik input clamp diode voltage 3.0 ? 1.2 v i i = ? 18 ma v ih minimum high level input voltage a n , plh in , dir, hd 4.5 ? 5.5 0.7 v cc v b n 4.5 ? 5.5 2.0 c n 4.5 ? 5.5 2.3 hlh in 4.5 ? 5.5 2.6 v il maximum low level input voltage a n , plh in , dir, hd 4.5 ? 5.5 0.3 v cc v b n 4.5 ? 5.5 0.8 c n 4.5 ? 5.5 0.8 hlh in 4.5 ? 5.5 1.6 ? vt minimum input hysteresis a n , plh in , dir, hd 4.5 ? 5.5 0.4 v v t + ? v t ? b n 4.5 ? 5.5 0.4 v t + ? v t ? c n 5.0 0.8 v t + ? v t ? hlh in 5.0 0.3 v t + ? v t ? v oh minimum high level output voltage a n , hlh 4.5 4.4 v i oh = ? 50 a 4.5 3.8 i oh = ? 8 ma b n , y n 4.5 3.73 i oh = ? 14 ma plh 4.5 4.45 i oh = ? 500 a
www.fairchildsemi.com 4 74vhc161284 dc electrical characteristics (continued) note 5: output impedance is measured with the output active low and active high (hd = high). note 6: this parameter is guaranteed but not tested, characterized only. note 7: power-down leakage to v cc is tested by simultaneously forcing all pins on the cable-side (b 1 ? b 8 , y 9 ? y 13 , plh, c 14 ? c 17 and hlh in to 5.5v and measuring the resulting i cc . symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) guaranteed limits v ol maximum low level output voltage a n , hlh 4.5 0.1 v i ol = 50 a 4.5 0.44 i ol = 8 ma b n , y n 4.5 0.77 i ol = 14 ma plh 4.5 0.7 i ol = 84 ma rd maximum output impedance b 1 ? b 8 , y 9 ? y 13 5.0 55 ? (note 5)(note 6) minimum output impedance b 1 ? b 8 , y 9 ? y 13 5.0 35 ? (note 5)(note 6) rp maximum pull-up resistance b 1 ? b 8 , y 9 ? y 13 , c 14 ? c 17 5.0 1650 ? minimum pull-up resistance b 1 ? b 8 , y 9 ? y 13 , c 14 ? c 17 5.0 1150 ? i ih maximum input current in high state a 9 ? a 13 , plh in , hd, dir, hlh in 5.5 1.0 a v i = 5.5v c 14 ? c 17 5.5 100 v i = 5.5v i il maximum input current in low state a 9 ? a 13 , plh in , hd, dir, hlh in 5.5 ? 1.0 av i = 0.0v c 14 ? c 17 5.5 ? 5.0 ma v i = 0.0v i ozh maximum output disable current a 1 ? a 8 5.5 20 a v o = 5.5v (high) b 1 ? b 8 5.5 100 v o = 5.5v i ozl maximum output disable current a 1 ? a 8 5.5 ? 20 av o = 0.0v (low) b 1 ? b 8 5.5 ? 5.0 ma i off power down output leakage b 1 ? b 8 , y 9 ? y 13 , plh 0.0 100 av o = 5.5v i off power down input leakage c 14 ? c 17 , hlh in 0.0 100 av i = 5.5v i off ? i cc power down leakage to v cc 0.0 250 a (note 7) i cc maximum supply current 5.5 70 ma v i = v cc or gnd
5 www.fairchildsemi.com 74vhc161284 ac electrical characteristics note 8: open drain note 9: t skew is measured for common edge output transitions and compares the measured propagation delay for a given path type. (i) a 1 ? a 8 to b 1 ? b 8 , a 9 ? y 13 to y 9 ? y 13 (ii) b 1 ? b 8 to a 1 ? a 8 (iii) c 14 ? c 17 to a 14 ? a 17 note 10: this parameter is guaranteed but not tested, characterized only. capacitance (note 11) note 11: capacitance is measured at frequency = 1 mhz. symbol parameter t a = ? 40 c to + 85 c units figure number v cc = 4.5v ? 5.5v min max t phl a 1 ? a 8 to b 1 ? b 8 2.0 30.0 ns figure 1 t plh a 1 ? a 8 to b 1 ? b 8 2.0 30.0 ns figure 2 t phl b 1 ? b 8 to a 1 ? a 8 2.0 30.0 ns figure 3 t plh b 1 ? b 8 to a 1 ? a 8 2.0 30.0 ns figure 3 t phl a 9 ? a 13 to y 9 ? y 13 2.0 30.0 ns figure 1 t plh a 9 ? a 13 to y 9 ? y 13 2.0 30.0 ns figure 2 t phl c 14 ? c 17 to a 14 ? a 17 2.0 30.0 ns figure 3 t plh c 14 ? c 17 to a 14 ? a 17 2.0 30.0 ns figure 3 t skew lh-lh or hl-hl 6.0 ns (note 9) t phl plh in to plh 2.0 30.0 ns figure 1 t plh plh in to plh 2.0 30.0 ns figure 2 t phl hlh in to hlh 2.0 30.0 ns figure 3 t plh hlh in to hlh 2.0 30.0 ns figure 3 t phz output disable time 2.0 18.0 ns figure 7 t plz dir to a 1 ? a 8 2.0 18.0 t pzh output enable time 2.0 25.0 ns figure 8 t pzl dir to a 1 ? a 8 2.0 25.0 t phz output disable time 2.0 25.0 ns figure 9 t plz dir to b 1 ? b 8 2.0 25.0 t pen output enable time 2.0 28.0 ns figure 2 hd to b 1 ? b 8 , y 9 ? y 13 t pdis output disable time 2.0 28.0 ns figure 2 hd to b 1 ? b 8 , y 9 ? y 13 t pen ? t pdis output enable-output disable 20.0 ns t slew output slew rate t plh b 1 ? b 8 , y 9 ? y 13 0.05 0.40 v/ns figure 5 t phl 0.05 0.40 figure 4 t r , t f t rise and t fall 120 ns figure 6 b 1 ? b 8 , y 9 ? y 13 (note 8) 120 (note 10) symbol parameter typ units conditions c in input capacitance 5 pf v cc = 0.0v (hd, dir, a 9 ? a 13 , c 14 ? c 17 , plh in and hlh in ) c i/o i/o pin capacitance 12 pf v cc = 3.3v
www.fairchildsemi.com 6 74vhc161284 ac loading and waveforms pulse generator for all pulses: rate 1.0 mhz; z o 50 ? ; t f 2.5 ns, t r 2.5 ns. figure 1. t phl test load and waveforms a 1 ?a 8 to b 1 ?b 8 a 9 ?a 13 to y 9 ?y 13 plh in to plh figure 2. t plh , t pen , t pdis test load and waveforms a 1 ?a 8 to b 1 ?b 8 , a 9 ?a 13 to y 9 ?y 13 plh in to plh, hd to b 1 ?b 8 , y 9 ?y 13 , plh figure 3. t phl , t plh test load and waveforms b 1 ?b 8 to a 1 ?a 8 , c 14 ?c 17 to a 14 ?a 17 , hlh in to hlh
7 www.fairchildsemi.com 74vhc161284 ac loading and waveforms (continued) figure 4. t slew hl test load and waveforms a 1 ? a 8 to b 1 ? b 8 a 9 ? a 13 to y 9 ? y 13 figure 5. t slew lh test load and waveforms a 1 ? a 8 to b 1 ? b 8 a 9 ? a 13 to y 9 ? y 13 t r = output rise time, open drain t f = output fall time, open drain figure 6. t rise and t fall test load and waveforms for open drain outputs a 1 ? a 8 to b 1 ? b 8 , a 9 ? a 13 to y 9 ? y 13
www.fairchildsemi.com 8 74vhc161284 ac loading and waveforms (continued) figure 7. t phz and t plz test load and waveforms, dir to a 1 ? a 8 figure 8. t pzh and t pzl test load and waveforms, dir to a 1 ? a 8
9 www.fairchildsemi.com 74vhc161284 ac loading and waveforms (continued) figure 9. t phz and t plz test load and waveforms, dir to b 1 ? b 8
www.fairchildsemi.com 10 74vhc161284 physical dimensions inches (millimeters) unless otherwise noted 48-lead small shrink outline package (ssop), jedec mo-118, 0.300 wide package number ms48a
11 www.fairchildsemi.com 74vhc161284 ieee 1284 transceiver physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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